ADZS-21469-EZLITE【PDF 4/62 页】KIT EVAL EZ LITE ADSP-21469

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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

GENERAL DESCRIPTION

Preliminary Technical Data

The ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

SHARC ? processors are members of the SIMD SHARC family

of DSPs that feature Analog Devices' Super Harvard Architec-

ture. The processors are source code compatible with the

ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x

DSPs as well as with first generation ADSP-2106x SHARC pro-

cessors in SISD (single-instruction, single-data) mode. These

new processors are 32-bit/40-bit floating point processors opti-

Table 1. SHARC Family Features (Continued)

Feature

mized for high performance audio applications with its large

on-chip SRAM, multiple internal buses to eliminate I/O bottle-

necks, and an innovative digital applications interface (DAI).

Table 1. SHARC Family Features

IDP

Serial Ports

SRU

DDR2

Yes

8

2

Yes

Yes

8

2

Yes

Yes

8

2

Yes

Yes

8

2

Yes

Yes

8

2

Yes

Memory

Interface

Feature

UART

DAI and DPI

1

20/14

pins

1

20/14

pins

1

20/14

pins

1

20/14

pins

1

20/14

pins

Frequency

400

MHz

400

MHz

450

MHz

450

MHz

400

MHz

Link Ports

S/PDIF

2

1

2

1

2

1

2

1

2

1

RAM

5M bits 5M bits

5M bits 5M bits 5M bits

Transceiver

ROM

1

N/A

4M bits

4M bits N/A

N/A

AMI Interface

with 8-bit

Yes

Yes

Yes

Yes

Yes

Audio

No

Yes

Yes

No

No

Support

Decoders in

ROM

SPI

2

2

2

2

2

Pulse-Width

Yes

Yes

Yes

Yes

Yes

TWI

Yes

Yes

Yes

Yes

Yes

Modulation

Package

324-

324-

324-

324-

324-

S/PDIF

Yes

Yes

Yes

Yes

Yes

ball

PBGA

ball

PBGA

ball

PBGA

ball

PBGA

ball

PBGA

DTCP 2

Yes

Yes

No

No

No

SRC

128 dB

128 dB

128 dB

128 dB

128 dB

DDR2

1/2

1/2

1/2

1/2

1/2

Performance

Memory

Interface

DDR2

Memory Bus

Width

Direct DMA

CCLK

Max

16 bits

Yes

CCLK

Max

16 bits

Yes

CCLK

Max

16 bits

Yes

CCLK

Max

16 bits

Yes

CCLK

Max

16 bits

Yes

1

2

Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/post-processor algorithm combination support varies depending

upon the chip version and the system configurations. Please visit

www.analog.com for complete information.

The ADSP-21462W and ADSP-21465W processors provide the Digital Trans-

mission Content Protection protocol, a proprietary security protocol. Contact

from SPORTs

to External

Memory

your Analog Devices sales office for more information.

As shown in the functional block diagram on Page 1 , the

FIR

Accelerator

IIR

Accelerator

FFT

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

processor uses two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the processor achieves an instruction

cycle time of 2.22 ns at 450 MHz and 2.5 ns at 400 MHz. With

its SIMD computational hardware, the processors can perform

Accelerator

2.7 GFLOPS running at 450 MHz and 2.4 GFLOPS running at

MLB

Yes

Yes

No

No

Yes

400 MHz.

Interface

Rev. PrC

| Page 4 of 62 | January 2009

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